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system verilog Jobs near Palo Alto, CA

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Senior Design Engineer - CPU Execution Unit, ALU Logic Design
Posted 07/10/2024
Santa Clara, CA
Sunnyvale, CA
San Jose, CA
Cupertino, CA
Fremont, CA
Full-time
$180,000.00 - $300,000.00
Located in the San Francisco Bay Area, we are a semiconductor startup that is developing a processor which combines the functionality of a CPU, GPU, and TPU into one to handle heavy AI/ML workloads! W...
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  • Arithmetic Unit (ALU) logic design
  • processor pipeline designs
  • state of the art deep submicron technologies
  • low power design techniques
  • Verilog
Sr. Design Verification Engineer
Posted 04/02/2025
San Jose, CA
Full-time
$150,000.00 - $230,000.00
Sr. Design Verification Engineer Position Overview We are seeking a highly skilled Sr. Design Verification Engineer to join our dynamic team. The ideal candidate will have a strong background in verif...
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  • Design Verification
  • PCIe
  • CXL
  • UVM
  • System Verilog
Verification Engineer
Posted 01/29/2025
San Jose, CA
Full-time
$150,000.00 - $175,000.00
We are a well established semiconductor company focuseed in the area of SSD memory and IC solutions. As we grow we are looking to add to our team with a new Verification with experience in the verific...
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  • UVM
  • SOC
  • PCIe
  • Python
  • Systems Verilog
Sr. RTL Design Engineer - PCIe/CXL
Posted 02/18/2025
San Jose, CA
Full-time
$170,000.00 - $230,000.00
Sr. RTL Design Engineer - PCIe/CXL Position Overview We are seeking a highly skilled Sr. RTL Design Engineer with expertise in PCIe and RTL design to join our team. The successful candidate will be re...
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  • PCIe
  • RTL
  • RTL Design
  • CXL
  • Ethernet
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Sr. ASIC Design Engineer - RTL, PCIe, CXL
Posted 07/19/2023
San Jose, CA
Full-time
$175,000.00 - $225,000.00
Job Title: Sr. ASIC Design Engineer - RTL, PCIe, CXL Job Location: San Jose, CA Compensation: $175K - $225K+ base Depending on experience plus stock options! Requirements: RTL Design, ASIC Design,...
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  • ASIC Design
  • RTL Design
  • Microarchitecture
  • PCIe
  • CXL
Principal ASIC Design Engineer - RTL, PCIe, CXL
Posted 09/18/2023
San Jose, CA
Full-time
$180,000.00 - $240,000.00
Job Title: Principal ASIC Design Engineer - RTL, PCIe, CXL Job Location: San Jose, CA Compensation: $180K - $240K base Depending on experience plus stock options! Requirements: RTL Design, ASIC De...
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  • ASIC Design
  • RTL Design
  • Microarchitecture
  • PCIe
  • CXL
Senior FPGA Design Engineer (DSP/MIMO/Wireless) - Hybrid
Posted 03/29/2021
Los Angeles, CA
San Diego, CA
San Francisco, CA
Full-time
$150,000.00 - $200,000.00
Located in Los Angeles, CA, we are a small and nimble wireless communications company doing real R&D for advanced commercial + defense MANET radios! We are looking for a Senior FPGA Design Engineer w...
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  • FPGA Design
  • VHDL
  • Verilog
  • DSP
  • MIMO
 
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